TACO: Rapid Design Space Exploration for Protocol Processors

To meet the tightening requirements on network hardware, the design of programmable processors with networkoptimized hardware, that is, network or protocol processors, has recently attracted interest. In this paper we address the problem of evaluating different architectural configurations for such processors. The proposed methodology enables easy and fast experimentation with different protocol processor hardware architecture configurations to estimate their performance characteristics at early stages in the design process. We conclude the paper with an example of designing processors using the methodology.